This invention relates to semiconductor devices packaged in encapsulating materials, and more particularly, an encapsulation package for precision analog integrated circuit chips that reduces parameter offsets and improves manufacturing yields.
Plastic encapsulation of integrated circuits has generally provided the most cost-effective packaging technique for high-precision analog products. Typically, after wafer fabrication process and conversion to silicon dice, discrete chips are attached to a metal lead frame. Thereafter, wire bonds are connected at bond pads on the chip to their corresponding interconnection leads. A plastic molding compound is then applied to the chip unit to provide package encapsulation. High-precision and high-sensitivity analog ICs have long suffered considerable yield loss after being encapsulated in plastic packages as a result of package related mechanical stress effects. The exertion of mechanical stress on piezoelectric materials, such as silicon, generates small but noticeable offset voltages that are capable of altering unacceptably the electrical performance of the circuits.
To overcome this problem, it has been proposed to apply a coating polymer layer, such as silicone gel or polyimide, to form a buffer region between molding compound and underlying silicon chip, as described by Roberts, Jr. in U.S. Pat. No. 5,026,667. The application of the extra polymer buffer layer has suffered from lack of thickness control and unpredictable improvement problems, as well as added manufacturing costs.
To overcome these limitations, offset adjustment circuitry needs to be provided or additional connecting leads need to be reserved to allow adjustment to product specifications. Undesirably, the adjustment circuitry requires additional silicon area and the additional leads require additional package spare pins and longer test times. Unfortunately, all of the above add significant manufacturing costs to the integrated circuits. Accordingly, a more cost-effective approach to alleviate the above shortcomings has been a long felt need. It is an object of this invention to solve that problem.
The present invention provides an embedded buffer volume between the package molding compound and the encapsulated silicon chip surface to avoid mechanical stress effects. The IC chip is fabricated in a conventional manner up to the contact pad-opening step. During contact pad opening, additional holes, smaller than the typical contact pad size, are opened on the second protection layer and followed by a subsequent removal of the first protection layer material under the holes using a wet chemical etch process. The resulting voids are bounded by the second protection layer on top and a metal layer at bottom, thereby providing a buffer region between encapsulating molding compound and the underlying stress-sensitive silicon areas in a plastic packaged IC chip. The layout of hole patterns is carefully considered such that the second protection layer provides enough mechanical strength to hold molding compound with the underlining first protection layer removed. The size of individual holes is selected to prevent the viscous molding compound from penetrating through the holes during the encapsulating process. Consequently, stress-sensitive circuitry areas in the resulting IC chip are insulated from the mechanical stress by the molding compound thereby achieving much smaller IC parameter offsets and higher product yields.
Accordingly, it is an object of present invention to provide improved semiconductor device structures for encapsulating analog IC chips in plastic packages.
Another object to the invention reside in reducing parameter offsets in encapsulated analog IC chips without additional circuitry or contact pins are required.
A further object is to provide improved performance on encapsulated IC chips through structural modification at the wafer level.